Digital data exchange device in a cdma system

ABSTRACT

The invention relates to a device for exchanging digital data between several sources and at least one hub in a CDMA system, characterised in that it comprises a number n of digital transmission/reception circuits ( 1 ) installed in parallel, each circuit ( 1 ) comprising a transmitter ( 2   i ) comprising means of generating an integer number N c  of codes that will be used for spectral spreading of data to be transmitted and a receiver ( 4   i ) comprising means ( 46, 48 ) of detecting the access of new sources to the CDMA system transmission channel and means ( 49 ) of generating synchronisation signals and power control signals corresponding to each detected new source.

TECHNICAL FIELD

[0001] The invention relates to a device for exchanging digital databetween several sources and at least one hub in a synchronous orquasi-synchronous CDMA (Code Division Multiple Access) system.

[0002] A synchronous CDMA system is composed of a set of transmittersusually called “modems”, and a receiver, usually called a “hub”. Theinformation is transmitted from the modems to the hub through an uplinkchannel and the information is transmitted from the hub to the modemsthrough a downlink channel. Several modems can start a transmissionsimultaneously. To make the link synchronous, information about eachmodem transmitted through the uplink channel must reach the hub in asynchronised manner.

[0003] During the transmission phase, one or several codes are allocatedto each modem so that they transmit its information at a speedcompatible with its demand. The codes used must be orthogonal with eachother such that inter-correlation noise is null when the codes aresynchronised. On reception, the hub decodes the received signal usingthe same codes as the modems in order to extract useful binaryinformation from the signal.

[0004] Synchronous reception of sent codes requires the use of a clockindicating the transmission frequency of binary symbols making up theinformation to be transmitted. This clock must be adjusted to apredetermined reference clock. Synchronisation of the various modemsthen consists of determining the offset between each transmitted codeand the reference clock and adjusting the symbol clock to the referenceclock.

[0005] The direct sequence spectrum spreading modulation technique iswell described in the specialised literature. For example, the followingbooks provide information about this technique:

[0006] “CDMA Principles of Spread Spectrum Communication” by Andrew J.VITERBI, Addison-Wesley Wireless Communications Series;

[0007] “Spread Spectrum Communication” by Marvin K. SIMON et al., vol.I, 1983, Computer Science Press;

[0008] “Spread Spectrum System”, R. C Dixon, John WILEY and Sons.

[0009] This technique is also described in some articles:

[0010] “Direct-Sequence Spread Spectrum with DPSK Modulation andDiversity for Indoor Wireless Communication”, published by MohsenKAVEHARAD and Bhashkar RAMAMURTHI, in the “IEEE Transactions” journal,vol. Com 35, No. 2, February 1987.

[0011] There are many advantages of the direct sequence spectrumspreading technique. Following are some examples of these advantages:

[0012] discretion: the discretion is related to spreading of informationtransmitted on a wide frequency band; the result is a low spectraldensity of the transmitted power;

[0013] multiple access: several direct sequence spectrum spreadingconnections may share the same frequency band using orthogonalpseudo-random spreading sequences (codes with an inter-correlationfunction that has very low residual noise for all offsets);

[0014] good cohabitation with conventional narrow band communications;the same frequency band may be shared by systems using a narrow bandmodulation and systems using a wide band modulation; narrow bandcommunications only experience a small increase in the ambientradioelectric noise, which is particularly weak when the length of thesequence is greater; spectrum spreading modulations reject narrow bandmodulations due to the correlation operation carried out on reception;

[0015] difficulty of interception: direct sequence spectrum spreadingtransmission is difficult to intercept due to the low spectral densityand due to the fact that the receiver must know the spreading sequencein order to be able to demodulate the data;

[0016] excellent behaviour in a multi-path environment: in this type ofenvironment, the radioelectric wave is propagated along multiple pathsthat involve reflection, diffraction and diffusion phenomena; moreover,it is not unusual if there is no longer a direct path stable in timebetween the transmitter and the receiver; this propagation alongmultiple paths induces parasite effects that tend to degrade thetransmission quality.

[0017] A large number of spreading codes are necessary, in order toobtain good flexibility in code allocation and a good robustness of thetransmission system with regard to pulse noise.

[0018] State of the Art

[0019] CDMA devices available on the market at the present time areincapable of generating a large number of spreading codes, and thedesign of a circuit capable of overcoming this limitation is expensiveand there are technical problems in manufacturing it. The processing tobe done by the hub is complex and requires a large number of operators,the number of which is proportional to the number of codes generated andthe length of each code. Furthermore, an increase in the number oftransmitters operating simultaneously requires greater synchronisationprecision due to the increase in inter-correlation noise.

[0020] Some examples of components according to prior art are:

[0021] the HFA 3860 component made by the Harris Company;

[0022] the SC2001 component made by the Sirius Communications Company.

[0023] The HFA 3860 circuit is essentially oriented towards apoint-to-point link and does not comprise any specific resources tomanage a link in a synchronous CDMA system.

[0024] The SC2001 system can only process two codes simultaneously.Furthermore, this circuit does not have any resource for management ofsymbol clocks, for estimating the transmission channel, demodulatingreceived codes, or calculating clock offset set values.

[0025] One purpose of the invention is to overcome the disadvantagesmentioned above by means of a device with an architecture that enablesthe use of a large number of spreading codes without affecting the speedof processing.

[0026] These purposes are achieved using a device comprising n digitaltransmission/reception circuits installed in parallel, each circuitcomprising a transmitter comprising means for generating an integernumber N_(c) of codes that will be used for spectral spreading of datato be transmitted and a receiver comprising means of detecting theaccess of new sources to the CDMA system transmission channel and meansof generating synchronisation signals and power control signalscorresponding to each detected new source.

[0027] According to the invention, each receiver comprises an inputstage, an acquisition management stage and a traffic management stage,the said input stage receiving a clock signal rx_ck with frequency f andoutputting this clock signal rx-ck to the traffic management stage andthe clock signal (rx_ck/n) with frequency f/n to the acquisitionmanagement stage such that each acquisition management stage processesone among n samples of received data.

[0028] According to the invention, the device also comprises a switchingcircuit to orient one among n data to be transmitted to eachtransmitter, an adder circuit for adding signals at the output of thesaid transmitters before transmission, a first calculation circuit foranalysing signals output from the acquisition management stages todetermine power and clock offset information, a second calculationcircuit for analysing signals output from the traffic management moduleto determine received binary data and clock offset information.

[0029] According to the invention, each input stage comprises a receivedsignals shaping module, a pulse filter for limiting the received signalsspectrum and a filtered signals sampling module.

[0030] According to the invention, each transmitter comprises a firstmodule for generating binary spreading codes and a second module forgenerating at least one internal clock signal to synchronise receptionof symbols transmitted by a source.

[0031] According to the invention, each acquisition management stagecomprises a first differential demodulation module, a module generatingan acquisition signal representative of synchronisation signals andpower control signals corresponding to each new transmission source, agenerated acquisition signal processing module and a first clockmanagement module.

[0032] According to the invention, each traffic management stagecomprises a module for correlating previously processed data with codesassociated with these data, a module for differential demodulation ofcorrelated data, a calculation module that will determinesynchronisation signals and power control signals corresponding to eachdetected new transmission source.

[0033] According to the invention, the number n oftransmission/reception circuits is equal to four and the first modulegenerating spreading codes is programmed to generate 32 (thirty-two)spreading codes each comprising 128 pulses with duration T_(c).

[0034] According to the invention, each acquisition management moduleprocesses a spreading code with 128 pulses.

[0035] According to the invention, the device comprises a displaymodule.

[0036] Other characteristics and advantages of the invention will becomeclearer after reading the following description given as anon-limitative example with reference to the attached figures, in which:

[0037]FIG. 1 shows a general layout of the device according to theinvention;

[0038]FIG. 2 shows a block diagram of a transmission/reception circuitintegrated into the device shown in FIG. 1;

[0039]FIG. 1 shows a preferred embodiment of the invention in which adevice in a CDMA system for a digital data exchange between severalsources and at least one hub comprises four digitaltransmission/reception circuits 1 installed in parallel, each circuit 1comprising a transmitter 2 _(i) and a receiver 4 _(i).

[0040] With reference to FIG. 2, each transmitter 2 _(i) comprises adata input module 6 installed in cascade with a data parallelisationblock 8, a differential modulation block 10, a spreading block 12, asummation block 14 and a first pulse filter 16.

[0041] A first module 20 supplies thirty-two binary codes to thespreading block 12 to spread the symbols to be transmitted, and a secondmodule 22 generates an internal clock signal. The first module 20comprises a table 24 comprising several codes and a code allocation mask26 that selects codes used at the transmitter 2. The binary throughputof the transmitter 2 is directly related to the number of codesvalidated in the mask 26.

[0042] The receiver 4 comprises an input stage 27, an acquisitionmanagement stage 28 and a traffic management stage 29.

[0043] To achieve parallelisation, a switching circuit 30 (FIG. 1)routes one among n data to be transmitted to each transmitter 2 _(i),and the signals at the output from the said transmitters 2 _(i) areadded in an adder circuit 31 before being transmitted, a firstcalculation circuit 32 analyses the signals at the output from theacquisition management stages to determine power and clock offsetinformation, and a second calculation circuit 33 analyses signals at theoutput from the traffic management module 29 to determine the receivedbinary data and clock offset information.

[0044] The input stage 27 (FIG. 2) comprises a received signals shapingblock 32, a pulse filter 34 that is designed to limit the receivedsignals spectrum, and a sampling stage 36 of filtered signals. Thisinput stage 27 transmits firstly base band data that have already beenprocessed (rxa_i, rxa_q) to the acquisition management stage 28, thatextracts power and time offset information for the received symbols withrespect to the base clock (rx_ckref) of the receiver 4 from these data,and secondly data (rxt_i, rxt_q) at the traffic management stage 29 thatextracts transmitted binary data and power and time offset informationfor received symbols with respect to the base clock (rx_ckref) of thereceiver 4, from these data.

[0045] The input stage 27 receives a clock signal rx-ck with frequency fand outputs this clock signal rx_ck to the traffic management stage 28,and the clock signal (rx_ck/n) with frequency f/4 to the acquisitionmanagement stage 28. Thus, each acquisition management stage 28processes one data sample out of every four received data.

[0046] The acquisition management stage 28 comprises a firstdifferential demodulation module 44, an acquisition signal generationmodule 46, and a generated signal processing module 48. The processingdone by module 48 detects access of new sources to the transmissionchannel and generates synchronisation signals and power control signalscorresponding to each new detected source. A new local symbol clockmanagement block 49 is used to adjust detected new transmission sourcesto the base clock of the receiver 4 (rx_ckref).

[0047] The traffic management stage 29 comprises a correlation stage 50comprising a first channel M, a second channel E and a third channel L.The M, E and L channels transmit correlated data corr_m, corr_e andcorr_l respectively, to a second differential demodulation stage 52 thattransmits the demodulated data to a calculation stage 54 that determinessynchronisation signals and power control signals corresponding to eachdetected new transmission source. A second clock management block 58retrieves the clock signal generated by the first clock management block49.

[0048] A programming module 59 accessible through a simple interfacecomprising an address bus and a data bus is used to program operatingparameters of transmitters 2 _(i) and receivers 4 _(i).

[0049] In the embodiment illustrated in FIG. 2, the correlation stage 50comprises a bench of thirty-two sliding correlators that makescorrelations between base band information after formatting rx_i andrxt_q and traffic sequences supplied by a codes table 70 and a maskingmodule 72. The maximum length of correlation sequences is 128 chips.

[0050] Each transmitter 2 _(i) can be programmed either in ACQUISITIONmode or in TRAFFIC mode, and receivers 4 _(i) manage currentcommunications and new accesses in parallel.

[0051] Four modulation formats may be used during the transmission,namely BPSK (Binary Phase Shift Keying) DBPSK (Differential Binary PhaseShift Keying), SPSK (Quaternary Phase Shift Keying), and DQPS(Differential Quaternary Phase Shift Keying). The BPSK and QPSKmodulations are accessible by programming. In QPSK, two useful bits aretransmitted per symbol and per code, which means that incoming data needto be grouped in packets of two “I” and “Q” bits. In BPSK, a singleuseful bit is transmitted per symbol and per code. Incoming data arecopied to I and Q, therefore everything in the rest of the transmissionsequence takes place as if QPSK modulation was used.

[0052] The base PSK modulation can be transformed into DPSK modulationby a differential encoding process by simple programming. Binary datagrouped into symbols of two bits are coded differentially according tothe IEEE 802.11 and DVB standards.

[0053]FIG. 2 shows input and output data related to the transmitter 2:

[0054] With the exterior:

[0055] tx_ck: transmitter 2 base clock;

[0056] tx_resetb: initialisation command;

[0057] tx_off: interrupt transmission command;

[0058] tx_traffic: traffic or acquisition mode command;

[0059] tx_data: input binary data;

[0060] tx_ensymb: validate symbols command;

[0061] tx_endata: validate data command;

[0062] tx_ckdac: sampling clock for analogue-digital converters;

[0063] tx_i: channel I transmitter output;

[0064] tx_q: channel Q transmitter output;

[0065] With the receiver 4 input stage:

[0066] tx_iint: internal loop back from channel I transmitter output;

[0067] tx_iint: internal loop back from channel Q transmitter output.

[0068] On reception, the input stage 27 shapes the base band signals andtransmits them to the acquisition stage 28 and to the traffic stage 29.

[0069] The base functions of the input stage 27 are:

[0070] clock management;

[0071] generation of clocks for the acquisition management stage 28and-the traffic management stage 29;

[0072] shaping of base band signals;

[0073] filtering of pulses;

[0074] sampling of filtered signals and transfer the sampled signals andthe clock signals to acquisition management stage 28 and the trafficmanagement stage 29.

[0075] The inputs and outputs for this stage are:

[0076] With the exterior

[0077] rx_ck: receiver base clock 4;

[0078] rx_resetb: reset to zero for initialisation;

[0079] rx_i: the channel I receiver 4 input;

[0080] rxq: the channel Q receiver 4 input;

[0081] rx_ckadc: sample clock for analogue digital converters;

[0082] rx_satent: saturation in shaping of input data.

[0083] With transmitter 2

[0084] tx_iint: internal loop back of the output from the transmitter 2channel I;

[0085] txqint: internal loop back of the output from the transmitter 2channel Q;

[0086] With acquisition stage 28

[0087] rxa_ckint: acquisition stage base clock 28;

[0088] rxa_i: base band information for channel I;

[0089] rxa_q: base band information for channel Q.

[0090] With the traffic management stage 29

[0091] rx_ckint: base clock for the traffic management stage 29;

[0092] rxt_i: base band information for channel I;

[0093] rx_tq: base band information for channel Q.

[0094] During operation, each transmitter 2 _(i) is programmed togenerate thirty-two spreading codes, different from the codes of theother transmitters. The maximum duration of the generated codes is equalto 128 times the duration of a chip. Since a chip is in a binary state,it will be equal to “0” or 11111 for the elementary duration T_(c). Thebinary data to be coded with successive sequences of thirty-twogenerated codes are presented at the inputs of the first transmitter 2₁, the second transmitter 2 ₂, the third transmitter 2 ₃ and the fourthtransmitter 2 ₄ respectively.

[0095] The input stage 27 divides the reference clock frequency rx_refby four and outputs a clock signal rx_ref/4 with frequency f/4, totransmitters 2 ₁ to 2 ₄. This division function is done by programmingthe frequency f and the number n. A number is assigned to each circuit 1so that data can be switched by the switching circuit 30.

[0096] Oversampling of the signal received at the input stage 27 enableseach circuit 1 to process a 128-chip long spreading code with eightsamples per chip. The circuit that sends the highest power informationvalue necessarily processes the most central sample in the chip. Theresulting clock offset is used to adjust the corresponding transmitter,the clock division factor and the circuit number are integrated in theoffset calculation such that the transmitter can use the offset setvalue produced directly. Each acquisition management circuit comprises aprogrammable circuit to search for the maximum on the four power dataproduced by the four circuits 1.

1. Device for exchanging digital data between several sources and atleast one hub in a CDMA system, characterised in that the devicecomprises n digital transmission/reception circuits (1) installed inparallel, each circuit (1) comprising a transmitter (2 _(i)) comprisingmeans for generating an integer number N_(c) of codes that will be usedfor spectral spreading of data to be transmitted and a receiver (4 _(i))comprising means (46, 48) of detecting the access of new sources to theCDMA system transmission channel and means (49) of generatingsynchronisation signals and power control signals corresponding to eachdetected new source.
 2. Device according to claim 1, characterised inthat each receiver (4) comprises an input stage (27), an acquisitionmanagement stage (28) and a traffic management stage (29), the saidinput stage (27) receiving a base clock signal rx_ck with frequency fand outputting this clock signal rx-ck to the traffic management stage(29) and the clock signal (rx_ck/n) with frequency f/n to theacquisition management stage (28) such that each acquisition managementstage (28) processes one among n samples of received data.
 3. Deviceaccording to claim 2, characterised in that it also comprises aswitching circuit (30) to orient one among n data to be transmitted to atransmitter (2), an adder circuit for adding signals at the output ofthe said transmitters (2 _(i)) before transmission, a first calculationcircuit for analysing signals output from the acquisition managementstages (28) to determine power and clock offset information, a secondcalculation circuit that for analysing signals output from the trafficmanagement module (29) to determine received binary data and clockoffset information.
 4. Device according to claim 1, characterised inthat each input stage (27) comprises a received signals shaping module(32), a pulse filter (34) for limiting the received signals spectrum anda filtered signals sampling module (36).
 5. Device according to claim 1,characterised in that each transmitter (2 _(i)) comprises a first module(20) for generating binary spreading codes N_(c) and a second module(22) for generating at least one internal clock signal to synchronisereception of symbols transmitted by a source.
 6. Device according toclaim 3, characterised in that each acquisition management stage (28)comprises a first differential demodulation module (44), a module (46)generating an acquisition signal representative of synchronisationsignals and power control signals corresponding to each new transmissionsource, a generated acquisition signal processing module (48) and afirst clock management module (49).
 7. Device according to claim 3,characterised in that each traffic management stage (29) comprises amodule (50) for correlating previously processed data with codesassociated with these data, a second module (52) for differentialdemodulation of the correlated data, a calculation module (54) fordetermining synchronisation signals and power control signalscorresponding to each detected new transmission source.
 8. Deviceaccording to claim 5, characterised in that the number n oftransmission/reception circuits is equal to four and the number N_(c) ofspreading codes is equal to
 32. 9. Device according to claim 8,characterised in that each spreading code comprises 128 pulses.